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  <name>alliance</name>
  <arch>aarch64</arch>
  <version epoch="0" ver="5.0" rel="113.1"/>
  <checksum type="sha256" pkgid="YES">fc195443e93a393d0a522a0ee2f60aa6ab20258efc6da6446c4e8fb6af58485b</checksum>
  <summary>VLSI EDA System</summary>
  <description>Alliance is a complete set of free CAD tools and portable libraries for
VLSI design. It includes a VHDL compiler and simulator, logic synthesis
tools, and automatic place and route tools.

A complete set of portable CMOS libraries is provided, including a RAM
generator, a ROM generator and a data-path compiler.

Alliance is the result of more than ten years effort spent at ASIM department
of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

Alliance has been used for research projects such as the 875 000 transistors
StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL
Router.

You are kindly requested to mention
" Designed with alliance (c) LIP6, Sorbonne Université"
so as to spread the word about "alliance CAD system" and its development team.

Alliance provides CAD tools covering most of all the digital design flow:

 * VHDL Compilation and Simulation
 * Model checking and formal proof
 * RTL and Logic synthesis
 * Data-Path compilation
 * Macro-cells generation
 * Place and route
 * Layout edition
 * Netlist extraction and verification
 * Design rules checking</description>
  <packager></packager>
  <url>http://coriolis.lip6.fr/</url>
  <time file="1765453158" build="1765452882"/>
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    <file type="dir">/etc/alliance</file>
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    <file>/etc/alliance/cmos.graal</file>
    <file>/etc/alliance/cmos.lef</file>
    <file>/etc/alliance/cmos.rds</file>
    <file>/etc/alliance/prol.elp</file>
    <file>/etc/alliance/scn6m_deep_09.rds</file>
    <file>/etc/alliance/se_defaults.mac</file>
    <file>/etc/alliance/spimodel.cfg</file>
    <file>/etc/alliance/sxlib.scapin</file>
    <file>/etc/alliance/symbolic.rds</file>
    <file>/etc/alliance/xfsm.par</file>
    <file>/etc/alliance/xgra.par</file>
    <file>/etc/alliance/xpat.par</file>
    <file>/etc/alliance/xsch.par</file>
    <file>/etc/alliance/xvpn.par</file>
    <file>/etc/ld.so.conf.d/alliance.conf</file>
    <file>/etc/profile.d/alc_env.csh</file>
    <file>/etc/profile.d/alc_env.sh</file>
    <file>/usr/bin/a2def</file>
    <file>/usr/bin/a2lef</file>
    <file>/usr/bin/alcbanner</file>
    <file>/usr/bin/asimut</file>
    <file>/usr/bin/attila</file>
    <file>/usr/bin/b2f</file>
    <file>/usr/bin/boog</file>
    <file>/usr/bin/boom</file>
    <file>/usr/bin/cougar</file>
    <file>/usr/bin/def2a</file>
    <file>/usr/bin/dreal</file>
    <file>/usr/bin/druc</file>
    <file>/usr/bin/exp</file>
    <file>/usr/bin/flatbeh</file>
    <file>/usr/bin/flatlo</file>
    <file>/usr/bin/flatph</file>
    <file>/usr/bin/flatrds</file>
    <file>/usr/bin/fmi</file>
    <file>/usr/bin/fsp</file>
    <file>/usr/bin/genlib</file>
    <file>/usr/bin/genpat</file>
    <file>/usr/bin/graal</file>
    <file>/usr/bin/k2f</file>
    <file>/usr/bin/l2p</file>
    <file>/usr/bin/loon</file>
    <file>/usr/bin/lvx</file>
    <file>/usr/bin/m2e</file>
    <file>/usr/bin/mips_asm</file>
    <file>/usr/bin/moka</file>
    <file>/usr/bin/nero</file>
    <file>/usr/bin/ocp</file>
    <file>/usr/bin/pat2spi</file>
    <file>/usr/bin/pdv</file>
    <file>/usr/bin/proof</file>
    <file>/usr/bin/ring</file>
    <file>/usr/bin/s2r</file>
    <file>/usr/bin/scapin</file>
    <file>/usr/bin/scr</file>
    <file>/usr/bin/sxlib2lef</file>
    <file>/usr/bin/syf</file>
    <file>/usr/bin/vasy</file>
    <file>/usr/bin/x2y</file>
    <file>/usr/bin/xfsm</file>
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  <summary>VLSI EDA System</summary>
  <description>Alliance is a complete set of free CAD tools and portable libraries for
VLSI design. It includes a VHDL compiler and simulator, logic synthesis
tools, and automatic place and route tools.

A complete set of portable CMOS libraries is provided, including a RAM
generator, a ROM generator and a data-path compiler.

Alliance is the result of more than ten years effort spent at ASIM department
of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

Alliance has been used for research projects such as the 875 000 transistors
StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL
Router.

You are kindly requested to mention
" Designed with alliance (c) LIP6, Sorbonne Université"
so as to spread the word about "alliance CAD system" and its development team.

Alliance provides CAD tools covering most of all the digital design flow:

 * VHDL Compilation and Simulation
 * Model checking and formal proof
 * RTL and Logic synthesis
 * Data-Path compilation
 * Macro-cells generation
 * Place and route
 * Layout edition
 * Netlist extraction and verification
 * Design rules checking</description>
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  <url>http://coriolis.lip6.fr/</url>
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  <summary>VLSI EDA System</summary>
  <description>Alliance is a complete set of free CAD tools and portable libraries for
VLSI design. It includes a VHDL compiler and simulator, logic synthesis
tools, and automatic place and route tools.

A complete set of portable CMOS libraries is provided, including a RAM
generator, a ROM generator and a data-path compiler.

Alliance is the result of more than ten years effort spent at ASIM department
of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

Alliance has been used for research projects such as the 875 000 transistors
StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL
Router.

You are kindly requested to mention
" Designed with alliance (c) LIP6, Sorbonne Université"
so as to spread the word about "alliance CAD system" and its development team.

Alliance provides CAD tools covering most of all the digital design flow:

 * VHDL Compilation and Simulation
 * Model checking and formal proof
 * RTL and Logic synthesis
 * Data-Path compilation
 * Macro-cells generation
 * Place and route
 * Layout edition
 * Netlist extraction and verification
 * Design rules checking</description>
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  <summary>VLSI EDA System</summary>
  <description>Alliance is a complete set of free CAD tools and portable libraries for
VLSI design. It includes a VHDL compiler and simulator, logic synthesis
tools, and automatic place and route tools.

A complete set of portable CMOS libraries is provided, including a RAM
generator, a ROM generator and a data-path compiler.

Alliance is the result of more than ten years effort spent at ASIM department
of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

Alliance has been used for research projects such as the 875 000 transistors
StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL
Router.

You are kindly requested to mention
" Designed with alliance (c) LIP6, Sorbonne Université"
so as to spread the word about "alliance CAD system" and its development team.

Alliance provides CAD tools covering most of all the digital design flow:

 * VHDL Compilation and Simulation
 * Model checking and formal proof
 * RTL and Logic synthesis
 * Data-Path compilation
 * Macro-cells generation
 * Place and route
 * Layout edition
 * Netlist extraction and verification
 * Design rules checking</description>
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      <rpm:entry name="libgcc_s.so.1()(64bit)"/>
      <rpm:entry name="libgcc_s.so.1(GCC_3.0)(64bit)"/>
      <rpm:entry name="libm.so.6()(64bit)"/>
      <rpm:entry name="libm.so.6(GLIBC_2.2.5)(64bit)"/>
      <rpm:entry name="libm.so.6(GLIBC_2.29)(64bit)"/>
      <rpm:entry name="libstdc++.so.6()(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.8)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.11)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.15)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.18)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.21)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.29)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.32)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.9)(64bit)"/>
      <rpm:entry name="rtld(GNU_HASH)"/>
      <rpm:entry name="xorg-x11-fonts-misc"/>
      <rpm:entry name="libc.so.6(GLIBC_2.38)(64bit)"/>
    </rpm:requires>
    <file type="dir">/etc/alliance</file>
    <file>/etc/alliance/cmos.dreal</file>
    <file>/etc/alliance/cmos.graal</file>
    <file>/etc/alliance/cmos.lef</file>
    <file>/etc/alliance/cmos.rds</file>
    <file>/etc/alliance/prol.elp</file>
    <file>/etc/alliance/scn6m_deep_09.rds</file>
    <file>/etc/alliance/se_defaults.mac</file>
    <file>/etc/alliance/spimodel.cfg</file>
    <file>/etc/alliance/sxlib.scapin</file>
    <file>/etc/alliance/symbolic.rds</file>
    <file>/etc/alliance/xfsm.par</file>
    <file>/etc/alliance/xgra.par</file>
    <file>/etc/alliance/xpat.par</file>
    <file>/etc/alliance/xsch.par</file>
    <file>/etc/alliance/xvpn.par</file>
    <file>/etc/ld.so.conf.d/alliance.conf</file>
    <file>/etc/profile.d/alc_env.csh</file>
    <file>/etc/profile.d/alc_env.sh</file>
    <file>/usr/bin/a2def</file>
    <file>/usr/bin/a2lef</file>
    <file>/usr/bin/alcbanner</file>
    <file>/usr/bin/asimut</file>
    <file>/usr/bin/attila</file>
    <file>/usr/bin/b2f</file>
    <file>/usr/bin/boog</file>
    <file>/usr/bin/boom</file>
    <file>/usr/bin/cougar</file>
    <file>/usr/bin/def2a</file>
    <file>/usr/bin/dreal</file>
    <file>/usr/bin/druc</file>
    <file>/usr/bin/exp</file>
    <file>/usr/bin/flatbeh</file>
    <file>/usr/bin/flatlo</file>
    <file>/usr/bin/flatph</file>
    <file>/usr/bin/flatrds</file>
    <file>/usr/bin/fmi</file>
    <file>/usr/bin/fsp</file>
    <file>/usr/bin/genlib</file>
    <file>/usr/bin/genpat</file>
    <file>/usr/bin/graal</file>
    <file>/usr/bin/k2f</file>
    <file>/usr/bin/l2p</file>
    <file>/usr/bin/loon</file>
    <file>/usr/bin/lvx</file>
    <file>/usr/bin/m2e</file>
    <file>/usr/bin/mips_asm</file>
    <file>/usr/bin/moka</file>
    <file>/usr/bin/nero</file>
    <file>/usr/bin/ocp</file>
    <file>/usr/bin/pat2spi</file>
    <file>/usr/bin/pdv</file>
    <file>/usr/bin/proof</file>
    <file>/usr/bin/ring</file>
    <file>/usr/bin/s2r</file>
    <file>/usr/bin/scapin</file>
    <file>/usr/bin/scr</file>
    <file>/usr/bin/sxlib2lef</file>
    <file>/usr/bin/syf</file>
    <file>/usr/bin/vasy</file>
    <file>/usr/bin/x2y</file>
    <file>/usr/bin/xfsm</file>
    <file>/usr/bin/xgra</file>
    <file>/usr/bin/xpat</file>
    <file>/usr/bin/xsch</file>
    <file>/usr/bin/xvpn</file>
  </format>
</package>
<package type="rpm">
  <name>alliance-debuginfo</name>
  <arch>aarch64</arch>
  <version epoch="0" ver="5.0" rel="113.1"/>
  <checksum type="sha256" pkgid="YES">ee51cc25cf508fa0081719b813498b1c975dae4771a398c1d7daca713001aacd</checksum>
  <summary>Debug information for package alliance</summary>
  <description>This package provides debug information for package alliance.
Debug information is useful when developing applications that use this
package or when debugging this package.</description>
  <packager></packager>
  <url>http://coriolis.lip6.fr/</url>
  <time file="1765453158" build="1765452882"/>
  <size package="1597106" installed="6452820" archive="6507700"/>
  <location href="aarch64/alliance-debuginfo-5.0-113.1.aarch64.rpm"/>
  <format>
    <rpm:license>GPL-2.0-only</rpm:license>
    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
    <rpm:group>Development/Debug</rpm:group>
    <rpm:buildhost>i01-armsrv1</rpm:buildhost>
    <rpm:sourcerpm>alliance-5.0-113.1.src.rpm</rpm:sourcerpm>
    <rpm:header-range start="4504" end="76585"/>
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      <rpm:entry name="libFsm.so.1.0.4-5.0-113.1.aarch64.debug()(64bit)"/>
      <rpm:entry name="libFtl.so.1.0.4-5.0-113.1.aarch64.debug()(64bit)"/>
      <rpm:entry name="libFvh.so.1.0.4-5.0-113.1.aarch64.debug()(64bit)"/>
      <rpm:entry name="libLog.so.2.0.1-5.0-113.1.aarch64.debug()(64bit)"/>
      <rpm:entry name="libMgn.so.3.0.3-5.0-113.1.aarch64.debug()(64bit)"/>
      <rpm:entry name="libMlo.so.4.0.2-5.0-113.1.aarch64.debug()(64bit)"/>
      <rpm:entry name="libMlu.so.4.0.2-5.0-113.1.aarch64.debug()(64bit)"/>
      <rpm:entry name="libMph.so.4.0.2-5.0-113.1.aarch64.debug()(64bit)"/>
      <rpm:entry name="libMpu.so.4.0.2-5.0-113.1.aarch64.debug()(64bit)"/>
      <rpm:entry name="libMut.so.4.0.2-5.0-113.1.aarch64.debug()(64bit)"/>
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      <rpm:entry name="libRcn.so.4.0.2-5.0-113.1.aarch64.debug()(64bit)"/>
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      <rpm:entry name="libVex.so.1.0.3-5.0-113.1.aarch64.debug()(64bit)"/>
      <rpm:entry name="libVpn.so.1.0.5-5.0-113.1.aarch64.debug()(64bit)"/>
      <rpm:entry name="libVrd.so.3.0.4-5.0-113.1.aarch64.debug()(64bit)"/>
    </rpm:provides>
    <rpm:recommends>
      <rpm:entry name="alliance-debugsource(aarch-64)" flags="EQ" epoch="0" ver="5.0" rel="113.1"/>
    </rpm:recommends>
    <file>/usr/lib/debug/usr/bin/a2def-5.0-113.1.aarch64.debug</file>
    <file>/usr/lib/debug/usr/bin/alcbanner-5.0-113.1.aarch64.debug</file>
    <file>/usr/lib/debug/usr/bin/asimut-5.0-113.1.aarch64.debug</file>
    <file>/usr/lib/debug/usr/bin/b2f-5.0-113.1.aarch64.debug</file>
    <file>/usr/lib/debug/usr/bin/boog-5.0-113.1.aarch64.debug</file>
    <file>/usr/lib/debug/usr/bin/boom-5.0-113.1.aarch64.debug</file>
    <file>/usr/lib/debug/usr/bin/cougar-5.0-113.1.aarch64.debug</file>
    <file>/usr/lib/debug/usr/bin/def2a-5.0-113.1.aarch64.debug</file>
    <file>/usr/lib/debug/usr/bin/dreal-5.0-113.1.aarch64.debug</file>
    <file>/usr/lib/debug/usr/bin/druc-5.0-113.1.aarch64.debug</file>
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</package>
<package type="rpm">
  <name>alliance-debuginfo</name>
  <arch>x86_64</arch>
  <version epoch="0" ver="5.0" rel="124.1"/>
  <checksum type="sha256" pkgid="YES">6518d3b98700900926b6b87d68ee2bd6f21680cd79331fc8816856414d273e8b</checksum>
  <summary>Debug information for package alliance</summary>
  <description>This package provides debug information for package alliance.
Debug information is useful when developing applications that use this
package or when debugging this package.</description>
  <packager></packager>
  <url>http://coriolis.lip6.fr/</url>
  <time file="1782746736" build="1782746527"/>
  <size package="1596669" installed="6277692" archive="6331880"/>
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Debug sources are useful when developing applications that use this
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  <description>A FOSS EDA tool suite for physical design. Provides an integrated
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  <packager>Mazher Iqbal &lt;mazher@lip6.fr&gt;</packager>
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  <summary>Coriolis 2 EDA toolchain</summary>
  <description>A FOSS EDA tool suite for physical design. Provides an integrated
place &amp; route for ASICs. Support symbolic layout (Alliance) and
real layout (GDS). While mainly written in C++, it has an extensive
Python interface.</description>
  <packager>Mazher Iqbal &lt;mazher@lip6.fr&gt;</packager>
  <url>https://coriolis.lip6.fr/</url>
  <time file="1769367373" build="1769366369"/>
  <size package="9166241" installed="36308001" archive="36468104"/>
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      <rpm:entry name="coriolis-eda(x86-64)" flags="EQ" epoch="0" ver="2.5.5" rel="247.1.3e579e0b9"/>
      <rpm:entry name="libanabatic.so()(64bit)"/>
      <rpm:entry name="libanalog.so()(64bit)"/>
      <rpm:entry name="libbora.so()(64bit)"/>
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      <rpm:entry name="libconfiguration.so()(64bit)"/>
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      <rpm:entry name="liblefdef.so()(64bit)"/>
      <rpm:entry name="liblibrarymanager.so()(64bit)"/>
      <rpm:entry name="libpycrlcore.so()(64bit)"/>
      <rpm:entry name="libpytypemanager.so()(64bit)"/>
      <rpm:entry name="libtramontana.so()(64bit)"/>
      <rpm:entry name="libtutorial.so()(64bit)"/>
      <rpm:entry name="libunicorn.so()(64bit)"/>
      <rpm:entry name="libutils.so()(64bit)"/>
      <rpm:entry name="libviewer.so()(64bit)"/>
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      <rpm:entry name="libQt5Core.so.5(Qt_5.15)(64bit)"/>
      <rpm:entry name="libQt5Gui.so.5()(64bit)"/>
      <rpm:entry name="libQt5Gui.so.5(Qt_5)(64bit)"/>
      <rpm:entry name="libQt5PrintSupport.so.5()(64bit)"/>
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</package>
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  <name>coriolis-eda-debuginfo</name>
  <arch>aarch64</arch>
  <version epoch="0" ver="2.5.5" rel="231.1.7095794fb"/>
  <checksum type="sha256" pkgid="YES">7b1dfbe7a4307318675e1450efd34272bbef2ed8dc173d9a1c18a702252fac0c</checksum>
  <summary>Debug information for package coriolis-eda</summary>
  <description>This package provides debug information for package coriolis-eda.
Debug information is useful when developing applications that use this
package or when debugging this package.</description>
  <packager>Mazher Iqbal &lt;mazher@lip6.fr&gt;</packager>
  <url>https://coriolis.lip6.fr/</url>
  <time file="1767632087" build="1767630312"/>
  <size package="58891838" installed="227423511" archive="227450264"/>
  <location href="aarch64/coriolis-eda-debuginfo-2.5.5-231.1.7095794fb.aarch64.rpm"/>
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  <checksum type="sha256" pkgid="YES">a3a1a135cf98536409e2b813f32d2921f5b856fe623d2378864201a8c92d75aa</checksum>
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  <description>This package provides debug information for package coriolis-eda.
Debug information is useful when developing applications that use this
package or when debugging this package.</description>
  <packager>Mazher Iqbal &lt;mazher@lip6.fr&gt;</packager>
  <url>https://coriolis.lip6.fr/</url>
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Debug sources are useful when developing applications that use this
package or when debugging this package.</description>
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  <description>This package provides debug sources for package coriolis-eda.
Debug sources are useful when developing applications that use this
package or when debugging this package.</description>
  <packager>Mazher Iqbal &lt;mazher@lip6.fr&gt;</packager>
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Warning: This package is only a stub for now.</description>
  <packager>Mazher Iqbal &lt;mazher@lip6.fr&gt;</packager>
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* The Coriolis Core (CRL) infrastructure (C++).
* The dedicated C++/Python wrapper (Isobar,C/C++/Python). The Python
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* Some technical specifications.
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The GF180MCU  open source PDK  is a collaboration between  Google and
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The GF180MCU documentation can be found at &lt;https://gf180mcu-pdk.rtfd.io&gt;.</description>
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  <summary>Global Foundries 180 MCU open PDK</summary>
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The GF180MCU  open source PDK  is a collaboration between  Google and
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manufacturable at GlobalFoundries's facility  on their 0.18um 3.3V/6V
MCU process technology.

The GF180MCU documentation can be found at &lt;https://gf180mcu-pdk.rtfd.io&gt;.</description>
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Chips4Makers (c4m) standard cell library for GF 180 MCU technology</description>
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  <description>
130nm  BiCMOS Open  Source PDK,  dedicated for  Analog/Digital, Mixed
Signal and RF Design

IHP Open  Source PDK project  goal is to  provide a fully  open source
Process  Design Kit  and related  data, which  can be  used to  create
manufacturable  designs at  IHP’s facility.   As of  March 2023,  this
repository is targeting the SG13G2 process node</description>
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  <url>https://github.com/IHP-GmbH/IHP-Open-PDK</url>
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<package type="rpm">
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  <summary>IHP Open PDK SG13G2</summary>
  <description>
130nm  BiCMOS Open  Source PDK,  dedicated for  Analog/Digital, Mixed
Signal and RF Design

IHP Open  Source PDK project  goal is to  provide a fully  open source
Process  Design Kit  and related  data, which  can be  used to  create
manufacturable  designs at  IHP’s facility.   As of  March 2023,  this
repository is targeting the SG13G2 process node</description>
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  <url>https://github.com/IHP-GmbH/IHP-Open-PDK</url>
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    <rpm:buildhost>i04-ch4d</rpm:buildhost>
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      <rpm:entry name="python-unversioned-command"/>
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<package type="rpm">
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  <checksum type="sha256" pkgid="YES">1f4e4e5cd004b64dceb8a98ff56dd37f55c688111f72dc1e25118302ec6e79e7</checksum>
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Chips4Makers (c4m) standard cell library for IHP SG13G2 technology</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-ihpsg13g2-c4m</url>
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<package type="rpm">
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Chips4Makers (c4m) standard cell library for IHP SG13G2 technology</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-ihpsg13g2-c4m</url>
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<package type="rpm">
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  <description>
NSxLib2 symbolic library configured with target nodes
* IHP 130 sg13g2
* GF 180 MCU
* SkyWater 130</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-nsx2</url>
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      <rpm:entry name="python3-devel"/>
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</package>
<package type="rpm">
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  <version epoch="0" ver="2025.12.31" rel="7.1.d6bdb51"/>
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  <summary>NSxLib2 Symbolic Library for Coriolis</summary>
  <description>
NSxLib2 symbolic library configured with target nodes
* IHP 130 sg13g2
* GF 180 MCU
* SkyWater 130</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-nsx2</url>
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    <rpm:group>Unspecified</rpm:group>
    <rpm:buildhost>i02-armsrv1</rpm:buildhost>
    <rpm:sourcerpm></rpm:sourcerpm>
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<package type="rpm">
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  <checksum type="sha256" pkgid="YES">2d2a1103c0969d44c3ac15fef3dccdf2c8a0920dc6760789a229854b52e38dd5</checksum>
  <summary>Chips4Makers PDK Master Library for Coriolis/SkyWater 130A</summary>
  <description>
Chips4Makers PDK Master cell libraries for Coriolis/SkyWater 130A</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-sky130-c4m</url>
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      <rpm:entry name="python-unversioned-command"/>
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</package>
<package type="rpm">
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  <summary>Chips4Makers PDK Master Library for Coriolis/SkyWater 130A</summary>
  <description>
Chips4Makers PDK Master cell libraries for Coriolis/SkyWater 130A</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-sky130-c4m</url>
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<package type="rpm">
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  <summary>KLayout, viewer and editor for mask layouts</summary>
  <description>Mask layout viewer and editor for the chip design engineer.

For details see README.md</description>
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  <url>http://www.klayout.de</url>
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  <location href="aarch64/klayout-0.30.3-1.1.6ad326e80.aarch64.rpm"/>
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  <description>Mask layout viewer and editor for the chip design engineer.

For details see README.md</description>
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  <url>http://www.klayout.de</url>
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For details see README.md</description>
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For details see README.md</description>
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      <rpm:entry name="qt5-qtbase" flags="GE" epoch="0" ver="5.15.9"/>
      <rpm:entry name="qt5-qtmultimedia" flags="GE" epoch="0" ver="5.15.9"/>
      <rpm:entry name="qt5-qtsvg" flags="GE" epoch="0" ver="5.15.9"/>
      <rpm:entry name="qt5-qttools" flags="GE" epoch="0" ver="5.15.9"/>
      <rpm:entry name="qt5-qttools-devel" flags="GE" epoch="0" ver="5.15.9"/>
      <rpm:entry name="qt5-qtxmlpatterns" flags="GE" epoch="0" ver="5.15.9"/>
      <rpm:entry name="ruby"/>
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    <file>/usr/bin/klayout</file>
    <file>/usr/bin/strm2cif</file>
    <file>/usr/bin/strm2dxf</file>
    <file>/usr/bin/strm2gds</file>
    <file>/usr/bin/strm2gdstxt</file>
    <file>/usr/bin/strm2lstr</file>
    <file>/usr/bin/strm2mag</file>
    <file>/usr/bin/strm2oas</file>
    <file>/usr/bin/strm2txt</file>
    <file>/usr/bin/strmclip</file>
    <file>/usr/bin/strmcmp</file>
    <file>/usr/bin/strmrun</file>
    <file>/usr/bin/strmxor</file>
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</package>
<package type="rpm">
  <name>libngspice</name>
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  <summary>Shared libraries for ngspice</summary>
  <description>Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
is based on three open source software packages: Spice3f5, Cider1b1
and Xspice. This package contains the shared libraries.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
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<package type="rpm">
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  <summary>Shared libraries for ngspice</summary>
  <description>Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
is based on three open source software packages: Spice3f5, Cider1b1
and Xspice. This package contains the shared libraries.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
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<package type="rpm">
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  <description>This package provides debug information for package libngspice.
Debug information is useful when developing applications that use this
package or when debugging this package.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
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<package type="rpm">
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  <summary>Debug information for package libngspice</summary>
  <description>This package provides debug information for package libngspice.
Debug information is useful when developing applications that use this
package or when debugging this package.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
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<package type="rpm">
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  <summary>Development files for ngspice</summary>
  <description>Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
is based on three open source software packages: Spice3f5, Cider1b1
and Xspice. This package contains the development files.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
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<package type="rpm">
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  <summary>Development files for ngspice</summary>
  <description>Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
is based on three open source software packages: Spice3f5, Cider1b1
and Xspice. This package contains the development files.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
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<package type="rpm">
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  <summary>A very capable VLSI layout tool</summary>
  <description>Magic is a venerable VLSI layout tool. Magic VLSI remains
popular with universities and small companies.

Magic is widely cited as being the easiest tool to use for
circuit layout, even for people who ultimately rely on commercial
tools for their product design flow.</description>
  <packager></packager>
  <url>http://opencircuitdesign.com/magic/index.html</url>
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      <rpm:entry name="libXi-devel"/>
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<package type="rpm">
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  <summary>A very capable VLSI layout tool</summary>
  <description>Magic is a venerable VLSI layout tool. Magic VLSI remains
popular with universities and small companies.

Magic is widely cited as being the easiest tool to use for
circuit layout, even for people who ultimately rely on commercial
tools for their product design flow.</description>
  <packager></packager>
  <url>http://opencircuitdesign.com/magic/index.html</url>
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<package type="rpm">
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  <description>This package contains the documentation of magic in the postscript
and some tutorials.</description>
  <packager></packager>
  <url>http://opencircuitdesign.com/magic/index.html</url>
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  <summary>Mixed-level, Mixed-signal Circuit Simulator Based on spice3f5</summary>
  <description>Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
is based on three open source software packages: Spice3f5, Cider1b1
and Xspice.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
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</package>
<package type="rpm">
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  <summary>Mixed-level, Mixed-signal Circuit Simulator Based on spice3f5</summary>
  <description>Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
is based on three open source software packages: Spice3f5, Cider1b1
and Xspice.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
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      <rpm:entry name="libgomp.so.1(GOMP_2.0)(64bit)"/>
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<package type="rpm">
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  <summary>Mixed-level, Mixed-signal Circuit Simulator Based on spice3f5</summary>
  <description>Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
is based on three open source software packages: Spice3f5, Cider1b1
and Xspice.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
  <time file="1761581938" build="1761580874"/>
  <size package="2412936" installed="7024480" archive="7032924"/>
  <location href="aarch64/ngspice-44.2-7.1.aarch64.rpm"/>
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</package>
<package type="rpm">
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  <arch>src</arch>
  <version epoch="0" ver="44.2" rel="7.1"/>
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  <summary>Mixed-level, Mixed-signal Circuit Simulator Based on spice3f5</summary>
  <description>Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
is based on three open source software packages: Spice3f5, Cider1b1
and Xspice.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
  <time file="1761581939" build="1761580874"/>
  <size package="11024742" installed="11203904" archive="11204288"/>
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      <rpm:entry name="libngspice-devel" flags="EQ" epoch="0" ver="44.2" rel="7.1"/>
      <rpm:entry name="ngspice-debuginfo" flags="EQ" epoch="0" ver="44.2" rel="7.1"/>
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      <rpm:entry name="libX11"/>
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      <rpm:entry name="libXmu-devel"/>
      <rpm:entry name="libtool"/>
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</package>
<package type="rpm">
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  <description>This package provides debug information for package ngspice.
Debug information is useful when developing applications that use this
package or when debugging this package.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
  <time file="1769370333" build="1769369364"/>
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      <rpm:entry name="debuginfo(build-id)" flags="EQ" epoch="0" ver="c70166e2a825841d36d6988fd8b10fcc24b3325b"/>
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      <rpm:entry name="ngspice-debuginfo" flags="EQ" epoch="0" ver="44.2" rel="10.1"/>
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    <rpm:recommends>
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    <file>/usr/lib/debug/usr/bin/ngspice-44.2-10.1.x86_64.debug</file>
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</package>
<package type="rpm">
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  <summary>Debug information for package ngspice</summary>
  <description>This package provides debug information for package ngspice.
Debug information is useful when developing applications that use this
package or when debugging this package.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
  <time file="1761581939" build="1761580874"/>
  <size package="6691617" installed="27301419" archive="27308792"/>
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    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
    <rpm:group>Development/Debug</rpm:group>
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      <rpm:entry name="debuginfo(build-id)" flags="EQ" epoch="0" ver="541865d48b41b9a58302ef702afed3b4383fa5e6"/>
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      <rpm:entry name="debuginfo(build-id)" flags="EQ" epoch="0" ver="9420b4314a089c25ce54f308f4e7ee0c804df27f"/>
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      <rpm:entry name="debuginfo(build-id)" flags="EQ" epoch="0" ver="a81e7a37f93bb2fa03f4f9d5cf3b3c3519c41665"/>
      <rpm:entry name="ngspice-debuginfo" flags="EQ" epoch="0" ver="44.2" rel="7.1"/>
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    <rpm:recommends>
      <rpm:entry name="ngspice-debugsource(aarch-64)" flags="EQ" epoch="0" ver="44.2" rel="7.1"/>
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    <file>/usr/lib/debug/usr/bin/ngspice-44.2-7.1.aarch64.debug</file>
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</package>
<package type="rpm">
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  <arch>x86_64</arch>
  <version epoch="0" ver="44.2" rel="10.1"/>
  <checksum type="sha256" pkgid="YES">835305fd6da5376aafaa542c0c5765bde0924facdd3530f322b789d8a83014bf</checksum>
  <summary>Debug sources for package ngspice</summary>
  <description>This package provides debug sources for package ngspice.
Debug sources are useful when developing applications that use this
package or when debugging this package.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
  <time file="1769370333" build="1769369364"/>
  <size package="2813173" installed="26600461" archive="27069316"/>
  <location href="x86_64/ngspice-debugsource-44.2-10.1.x86_64.rpm"/>
  <format>
    <rpm:license>BSD-2-Clause</rpm:license>
    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
    <rpm:group>Development/Debug</rpm:group>
    <rpm:buildhost>i02-ch2d</rpm:buildhost>
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    <rpm:provides>
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</package>
<package type="rpm">
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  <checksum type="sha256" pkgid="YES">b31469e972d93e84ac6dce841226c75e6511dffbbd4814445722a985bc092618</checksum>
  <summary>Debug sources for package ngspice</summary>
  <description>This package provides debug sources for package ngspice.
Debug sources are useful when developing applications that use this
package or when debugging this package.</description>
  <packager></packager>
  <url>https://ngspice.sourceforge.io</url>
  <time file="1761581939" build="1761580874"/>
  <size package="2813369" installed="26600461" archive="27069316"/>
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<package type="rpm">
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  <arch>aarch64</arch>
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  <summary>OpenVAF is a Next-Generation Verilog-A compiler</summary>
  <description>Circuit simulators play a critical role in the design of electrical circuits.
Accurate simulations enable circuit designers to validate circuit behavior
before actual fabrication happens, potentially saving significant re-design
costs.  The simulation of a circuit critically depends on the so-called compact
models and therefore:
* The accuracy of the compact-model equations
* The quality of the model parameters</description>
  <packager></packager>
  <url>https://openvaf.semimod.de/</url>
  <time file="1738937602" build="1738937543"/>
  <size package="18684971" installed="72145304" archive="72145556"/>
  <location href="aarch64/openvaf-23.5.0-5.1.aarch64.rpm"/>
  <format>
    <rpm:license>GPL-3.0-only</rpm:license>
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Accurate simulations enable circuit designers to validate circuit behavior
before actual fabrication happens, potentially saving significant re-design
costs.  The simulation of a circuit critically depends on the so-called compact
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* The accuracy of the compact-model equations
* The quality of the model parameters</description>
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  <description>Circuit simulators play a critical role in the design of electrical circuits.
Accurate simulations enable circuit designers to validate circuit behavior
before actual fabrication happens, potentially saving significant re-design
costs.  The simulation of a circuit critically depends on the so-called compact
models and therefore:
* The accuracy of the compact-model equations
* The quality of the model parameters</description>
  <packager></packager>
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  <description>Circuit simulators play a critical role in the design of electrical circuits.
Accurate simulations enable circuit designers to validate circuit behavior
before actual fabrication happens, potentially saving significant re-design
costs.  The simulation of a circuit critically depends on the so-called compact
models and therefore:
* The accuracy of the compact-model equations
* The quality of the model parameters</description>
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  <time file="1769369569" build="1769369538"/>
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<package type="rpm">
  <name>python3-coriolis-pdk-gf180mcu</name>
  <arch>noarch</arch>
  <version epoch="0" ver="2025.07.21" rel="6.1.bfa7190"/>
  <checksum type="sha256" pkgid="YES">3487460d4df080793c86fec72a4c2fc7c0e92c91083d704e865f8e6be77a6123</checksum>
  <summary>Global Foundries 180 MCU open PDK</summary>
  <description>
The GF180MCU  open source PDK  is a collaboration between  Google and
GlobalFoundries to  provide a  fully open  source process  design kit
(PDK)  and  related  resources  to enable  the  creation  of  designs
manufacturable at GlobalFoundries's facility  on their 0.18um 3.3V/6V
MCU process technology.

The GF180MCU documentation can be found at &lt;https://gf180mcu-pdk.rtfd.io&gt;.</description>
  <packager></packager>
  <url>https://github.com/google/gf180mcu-pdk.git</url>
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    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
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    <rpm:buildhost>i01-armsrv3</rpm:buildhost>
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</package>
<package type="rpm">
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  <arch>noarch</arch>
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  <checksum type="sha256" pkgid="YES">e67e03e2f9d8e934fbf488b242d581e8a40991b139b290a93bb851303f1dfb35</checksum>
  <summary>Global Foundries 180 MCU open PDK</summary>
  <description>
The GF180MCU  open source PDK  is a collaboration between  Google and
GlobalFoundries to  provide a  fully open  source process  design kit
(PDK)  and  related  resources  to enable  the  creation  of  designs
manufacturable at GlobalFoundries's facility  on their 0.18um 3.3V/6V
MCU process technology.

The GF180MCU documentation can be found at &lt;https://gf180mcu-pdk.rtfd.io&gt;.</description>
  <packager></packager>
  <url>https://github.com/google/gf180mcu-pdk.git</url>
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  <size package="397752079" installed="5128459595" archive="5134316484"/>
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</package>
<package type="rpm">
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  <checksum type="sha256" pkgid="YES">a015b810a8833888cfaedd361bcacfa263c1a8c5eebba95d342fc703fe8267f5</checksum>
  <summary>C4M Standard Cells for GF 180 MCU</summary>
  <description>
Chips4Makers (c4m) standard cell library for GF 180 MCU technology</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-gf180mcu-c4m</url>
  <time file="1769368635" build="1769368626"/>
  <size package="508226" installed="7628621" archive="7741644"/>
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    <rpm:buildhost>i02-ch2b</rpm:buildhost>
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      <rpm:entry name="/usr/bin/sh"/>
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    <file>/usr/lib64/python3.13/site-packages/pdks/gf180mcu_c4m/klayout/bin/drc_gf180mcu</file>
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    <file>/usr/lib64/python3.13/site-packages/pdks/gf180mcu_c4m/klayout/bin/lvs_gf180mcu</file>
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</package>
<package type="rpm">
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  <checksum type="sha256" pkgid="YES">45af3ba3f5336098aba8915d651842d92b72274f385268ac18c4f47c4dd3e220</checksum>
  <summary>C4M Standard Cells for GF 180 MCU</summary>
  <description>
Chips4Makers (c4m) standard cell library for GF 180 MCU technology</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-gf180mcu-c4m</url>
  <time file="1765544461" build="1765544450"/>
  <size package="508271" installed="7628622" archive="7741648"/>
  <location href="noarch/python3-coriolis-pdk-gf180mcu-c4m-2025.7.28-9.1.4d69c14.noarch.rpm"/>
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    <rpm:license>GPL-2.0-or-later</rpm:license>
    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
    <rpm:group>Unspecified</rpm:group>
    <rpm:buildhost>i01-armsrv3</rpm:buildhost>
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      <rpm:entry name="python-coriolis-pdk-gf180mcu-c4m" flags="EQ" epoch="0" ver="2025.7.28" rel="9.1.4d69c14"/>
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<package type="rpm">
  <name>python3-coriolis-pdk-ihpsg13g2</name>
  <arch>noarch</arch>
  <version epoch="0" ver="2024.10.15" rel="23.1.bfa7190"/>
  <checksum type="sha256" pkgid="YES">c0b963878e12b3000d54a86261b4bd74c3c96a975128121ca4ebe7f313ddd632</checksum>
  <summary>IHP Open PDK SG13G2</summary>
  <description>
130nm  BiCMOS Open  Source PDK,  dedicated for  Analog/Digital, Mixed
Signal and RF Design

IHP Open  Source PDK project  goal is to  provide a fully  open source
Process  Design Kit  and related  data, which  can be  used to  create
manufacturable  designs at  IHP’s facility.   As of  March 2023,  this
repository is targeting the SG13G2 process node</description>
  <packager></packager>
  <url>https://github.com/IHP-GmbH/IHP-Open-PDK</url>
  <time file="1737472814" build="1737472687"/>
  <size package="23022718" installed="189390838" archive="189751244"/>
  <location href="noarch/python3-coriolis-pdk-ihpsg13g2-2024.10.15-23.1.bfa7190.noarch.rpm"/>
  <format>
    <rpm:license>Apache-2.0</rpm:license>
    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
    <rpm:group>Unspecified</rpm:group>
    <rpm:buildhost>i01-armsrv2</rpm:buildhost>
    <rpm:sourcerpm>coriolis-pdk-ihpsg13g2-2024.10.15-23.1.bfa7190.src.rpm</rpm:sourcerpm>
    <rpm:header-range start="4504" end="252253"/>
    <rpm:provides>
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      <rpm:entry name="python3.13-coriolis-pdk-ihpsg13g2" flags="EQ" epoch="0" ver="2024.10.15" rel="23.1.bfa7190"/>
      <rpm:entry name="python3.13dist(coriolis-pdk-ihpsg13g2)" flags="EQ" epoch="0" ver="2024.10.15"/>
      <rpm:entry name="python3dist(coriolis-pdk-ihpsg13g2)" flags="EQ" epoch="0" ver="2024.10.15"/>
    </rpm:provides>
    <rpm:requires>
      <rpm:entry name="/usr/bin/python3"/>
      <rpm:entry name="python(abi)" flags="EQ" epoch="0" ver="3.13"/>
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</package>
<package type="rpm">
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  <arch>x86_64</arch>
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  <checksum type="sha256" pkgid="YES">269789f60ae6eaf3396caee9d3db4492b2a8788769a40a835697edc467ef3b53</checksum>
  <summary>IHP Open PDK SG13G2</summary>
  <description>
130nm  BiCMOS Open  Source PDK,  dedicated for  Analog/Digital, Mixed
Signal and RF Design

IHP Open  Source PDK project  goal is to  provide a fully  open source
Process  Design Kit  and related  data, which  can be  used to  create
manufacturable  designs at  IHP’s facility.   As of  March 2023,  this
repository is targeting the SG13G2 process node</description>
  <packager></packager>
  <url>https://github.com/IHP-GmbH/IHP-Open-PDK</url>
  <time file="1771413520" build="1771413377"/>
  <size package="48221400" installed="349151968" archive="349672624"/>
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    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
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    <rpm:buildhost>i04-ch4d</rpm:buildhost>
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      <rpm:entry name="python3.13dist(coriolis-pdk-ihpsg13g2)" flags="EQ" epoch="0" ver="2025.12.27"/>
      <rpm:entry name="python3dist(coriolis-pdk-ihpsg13g2)" flags="EQ" epoch="0" ver="2025.12.27"/>
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    <rpm:requires>
      <rpm:entry name="/usr/bin/bash"/>
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</package>
<package type="rpm">
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  <checksum type="sha256" pkgid="YES">02f5f44dda096d294d534489ae72b023bca0b3a57f990494d5fd22c4dea57dd5</checksum>
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  <description>
Chips4Makers (c4m) standard cell library for IHP SG13G2 technology</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-ihpsg13g2-c4m</url>
  <time file="1767138710" build="1767138699"/>
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      <rpm:entry name="python(abi)" flags="EQ" epoch="0" ver="3.13"/>
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    <file>/usr/lib64/python3.13/site-packages/pdks/ihpsg13g2_c4m/libs.tech/klayout/bin/drc_C4M.IHPSG13G2</file>
    <file>/usr/lib64/python3.13/site-packages/pdks/ihpsg13g2_c4m/libs.tech/klayout/bin/extract_C4M.IHPSG13G2</file>
    <file>/usr/lib64/python3.13/site-packages/pdks/ihpsg13g2_c4m/libs.tech/klayout/bin/lvs_C4M.IHPSG13G2</file>
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<package type="rpm">
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  <checksum type="sha256" pkgid="YES">27603f2a1753430b7f5bb1aca9d920b39495224da5ddee6e1e7081f6b05d59f8</checksum>
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  <description>
Chips4Makers (c4m) standard cell library for IHP SG13G2 technology</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-ihpsg13g2-c4m</url>
  <time file="1769368839" build="1769368828"/>
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    <file>/usr/lib64/python3.13/site-packages/pdks/ihpsg13g2_c4m/libs.tech/klayout/bin/extract_C4M.IHPSG13G2</file>
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<package type="rpm">
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  <version epoch="0" ver="2025.12.31" rel="10.1"/>
  <checksum type="sha256" pkgid="YES">d815ddf74cf3f3aa844a1d780347516727dc1df44d832cff771537982ec1d2c6</checksum>
  <summary>NSxLib2 Symbolic Library for Coriolis</summary>
  <description>
NSxLib2 symbolic library configured with target nodes
* IHP 130 sg13g2
* GF 180 MCU
* SkyWater 130</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-nsx2</url>
  <time file="1782747983" build="1782747825"/>
  <size package="101999722" installed="514961716" archive="515184240"/>
  <location href="x86_64/python3-coriolis-pdk-nsx2-2025.12.31-10.1.x86_64.rpm"/>
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    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
    <rpm:group>Unspecified</rpm:group>
    <rpm:buildhost>i01-ch2a</rpm:buildhost>
    <rpm:sourcerpm>coriolis-pdk-nsx2-2025.12.31-10.1.src.rpm</rpm:sourcerpm>
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</package>
<package type="rpm">
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  <checksum type="sha256" pkgid="YES">ff60a78f8cf299883ecc4022f6d4aa08f62245b758153511b8332414a1194274</checksum>
  <summary>NSxLib2 Symbolic Library for Coriolis</summary>
  <description>
NSxLib2 symbolic library configured with target nodes
* IHP 130 sg13g2
* GF 180 MCU
* SkyWater 130</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-nsx2</url>
  <time file="1766008819" build="1766008559"/>
  <size package="101919924" installed="514961717" archive="515184244"/>
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  <format>
    <rpm:license>GPL-2.0-or-later</rpm:license>
    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
    <rpm:group>Unspecified</rpm:group>
    <rpm:buildhost>i02-armsrv1</rpm:buildhost>
    <rpm:sourcerpm>coriolis-pdk-nsx2-2025.12.31-7.1.d6bdb51.src.rpm</rpm:sourcerpm>
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    <rpm:requires>
      <rpm:entry name="python(abi)" flags="EQ" epoch="0" ver="3.13"/>
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</package>
<package type="rpm">
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  <checksum type="sha256" pkgid="YES">eda275b550da40aafefab50e66d741c313da2fb799503b95ce06d38df57f5a91</checksum>
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  <description>
Chips4Makers PDK Master cell libraries for Coriolis/SkyWater 130A</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-sky130-c4m</url>
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    <file>/usr/lib64/python3.13/site-packages/pdks/sky130_c4m/libs.tech/klayout/bin/drc_C4M.Sky130</file>
    <file>/usr/lib64/python3.13/site-packages/pdks/sky130_c4m/libs.tech/klayout/bin/extract_C4M.Sky130</file>
    <file>/usr/lib64/python3.13/site-packages/pdks/sky130_c4m/libs.tech/klayout/bin/lvs_C4M.Sky130</file>
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</package>
<package type="rpm">
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  <checksum type="sha256" pkgid="YES">a17c57cf3877c55f597da1a3ad91e6f5c112103b21650de143c206cb555635ed</checksum>
  <summary>Chips4Makers PDK Master Library for Coriolis/SkyWater 130A</summary>
  <description>
Chips4Makers PDK Master cell libraries for Coriolis/SkyWater 130A</description>
  <packager></packager>
  <url>https://github.com/lip6/coriolis-pdk-sky130-c4m</url>
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    <file>/usr/lib64/python3.13/site-packages/pdks/sky130_c4m/libs.tech/klayout/bin/lvs_C4M.Sky130</file>
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  <description>sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005),
with an emphasis on supporting synthesizable language constructs.
  The primary goal of this project is to create a completely free and
open-source tool for converting SystemVerilog to Verilog. While methods
for performing this conversion already exist, they generally either rely
on commercial tools, or are limited in scope.
  This project was originally developed to target Yosys, and so allows for
disabling the conversion of (passing through) those SystemVerilog features
that Yosys supports.</description>
  <packager></packager>
  <url>https://github.com/zachjs/sv2v/</url>
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    <rpm:group>Applications/Engineering</rpm:group>
    <rpm:buildhost>i02-armsrv1</rpm:buildhost>
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      <rpm:entry name="rtld(GNU_HASH)"/>
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    <file>/usr/bin/sv2v</file>
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<package type="rpm">
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  The primary goal of this project is to create a completely free and
open-source tool for converting SystemVerilog to Verilog. While methods
for performing this conversion already exist, they generally either rely
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  This project was originally developed to target Yosys, and so allows for
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  The primary goal of this project is to create a completely free and
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for performing this conversion already exist, they generally either rely
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  This project was originally developed to target Yosys, and so allows for
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  The  advent   of  semiconductor  fabrication  technologies   now  allows  high
performance in complex integrated circuits.
  With the increasing complexity of these circuits, static timing analysis (STA)
has  revealed  itself  as  the  only  feasible  method  ensuring  that  expected
performances are actually obtained.
  In addition, signal integrity (SI) issues due to crosstalk play a crucial role
in performance and reliability of these  systems, and must be taken into account
during the timing analysis.
  However, performance  achievement not  only lies in  fabrication technologies,
but also  in the way circuits  are designed.  Very high  performance designs are
obtained with semi or full-custom designs techniques.
  The HITAS platform provides advanced STA and SI solutions at transistor level.
It has been  built-up in order to allow engineers to  ensure complete timing and
SI coverage on their digital custom  designs, as well as IP-reuse through timing
abstraction.
  Furthermore,  hierarchy  handling  through  transparent  timing  views  allows
full-chip verification, with virtually no limit of capacity in design size.</description>
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  The  advent   of  semiconductor  fabrication  technologies   now  allows  high
performance in complex integrated circuits.
  With the increasing complexity of these circuits, static timing analysis (STA)
has  revealed  itself  as  the  only  feasible  method  ensuring  that  expected
performances are actually obtained.
  In addition, signal integrity (SI) issues due to crosstalk play a crucial role
in performance and reliability of these  systems, and must be taken into account
during the timing analysis.
  However, performance  achievement not  only lies in  fabrication technologies,
but also  in the way circuits  are designed.  Very high  performance designs are
obtained with semi or full-custom designs techniques.
  The HITAS platform provides advanced STA and SI solutions at transistor level.
It has been  built-up in order to allow engineers to  ensure complete timing and
SI coverage on their digital custom  designs, as well as IP-reuse through timing
abstraction.
  Furthermore,  hierarchy  handling  through  transparent  timing  views  allows
full-chip verification, with virtually no limit of capacity in design size.</description>
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  The  advent   of  semiconductor  fabrication  technologies   now  allows  high
performance in complex integrated circuits.
  With the increasing complexity of these circuits, static timing analysis (STA)
has  revealed  itself  as  the  only  feasible  method  ensuring  that  expected
performances are actually obtained.
  In addition, signal integrity (SI) issues due to crosstalk play a crucial role
in performance and reliability of these  systems, and must be taken into account
during the timing analysis.
  However, performance  achievement not  only lies in  fabrication technologies,
but also  in the way circuits  are designed.  Very high  performance designs are
obtained with semi or full-custom designs techniques.
  The HITAS platform provides advanced STA and SI solutions at transistor level.
It has been  built-up in order to allow engineers to  ensure complete timing and
SI coverage on their digital custom  designs, as well as IP-reuse through timing
abstraction.
  Furthermore,  hierarchy  handling  through  transparent  timing  views  allows
full-chip verification, with virtually no limit of capacity in design size.</description>
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  <description>STATIC TIMING ANALYSIS
  The  advent   of  semiconductor  fabrication  technologies   now  allows  high
performance in complex integrated circuits.
  With the increasing complexity of these circuits, static timing analysis (STA)
has  revealed  itself  as  the  only  feasible  method  ensuring  that  expected
performances are actually obtained.
  In addition, signal integrity (SI) issues due to crosstalk play a crucial role
in performance and reliability of these  systems, and must be taken into account
during the timing analysis.
  However, performance  achievement not  only lies in  fabrication technologies,
but also  in the way circuits  are designed.  Very high  performance designs are
obtained with semi or full-custom designs techniques.
  The HITAS platform provides advanced STA and SI solutions at transistor level.
It has been  built-up in order to allow engineers to  ensure complete timing and
SI coverage on their digital custom  designs, as well as IP-reuse through timing
abstraction.
  Furthermore,  hierarchy  handling  through  transparent  timing  views  allows
full-chip verification, with virtually no limit of capacity in design size.</description>
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  <url>https://coriolis.lip6.fr/</url>
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  <description>STATIC TIMING ANALYSIS
  The  advent   of  semiconductor  fabrication  technologies   now  allows  high
performance in complex integrated circuits.
  With the increasing complexity of these circuits, static timing analysis (STA)
has  revealed  itself  as  the  only  feasible  method  ensuring  that  expected
performances are actually obtained.
  In addition, signal integrity (SI) issues due to crosstalk play a crucial role
in performance and reliability of these  systems, and must be taken into account
during the timing analysis.
  However, performance  achievement not  only lies in  fabrication technologies,
but also  in the way circuits  are designed.  Very high  performance designs are
obtained with semi or full-custom designs techniques.
  The HITAS platform provides advanced STA and SI solutions at transistor level.
It has been  built-up in order to allow engineers to  ensure complete timing and
SI coverage on their digital custom  designs, as well as IP-reuse through timing
abstraction.
  Furthermore,  hierarchy  handling  through  transparent  timing  views  allows
full-chip verification, with virtually no limit of capacity in design size.</description>
  <packager></packager>
  <url>https://coriolis.lip6.fr/</url>
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      <rpm:entry name="tas-yagle" flags="EQ" epoch="0" ver="3.4.6" rel="170.1.02c7f67"/>
    </rpm:requires>
  </format>
</package>
<package type="rpm">
  <name>tas-yagle-doc</name>
  <arch>noarch</arch>
  <version epoch="0" ver="3.4.6" rel="178.1.742cf58"/>
  <checksum type="sha256" pkgid="YES">794416329ed0229e2ea6fb27fdef90b14d3064bab7a63bafdd56028b19afcce6</checksum>
  <summary>Documentation &amp; Tutorials for Tas/Yagle</summary>
  <description>STATIC TIMING ANALYSIS
  The  advent   of  semiconductor  fabrication  technologies   now  allows  high
performance in complex integrated circuits.
  With the increasing complexity of these circuits, static timing analysis (STA)
has  revealed  itself  as  the  only  feasible  method  ensuring  that  expected
performances are actually obtained.
  In addition, signal integrity (SI) issues due to crosstalk play a crucial role
in performance and reliability of these  systems, and must be taken into account
during the timing analysis.
  However, performance  achievement not  only lies in  fabrication technologies,
but also  in the way circuits  are designed.  Very high  performance designs are
obtained with semi or full-custom designs techniques.
  The HITAS platform provides advanced STA and SI solutions at transistor level.
It has been  built-up in order to allow engineers to  ensure complete timing and
SI coverage on their digital custom  designs, as well as IP-reuse through timing
abstraction.
  Furthermore,  hierarchy  handling  through  transparent  timing  views  allows
full-chip verification, with virtually no limit of capacity in design size.</description>
  <packager></packager>
  <url>https://coriolis.lip6.fr/</url>
  <time file="1769369896" build="1769369748"/>
  <size package="12984488" installed="71311230" archive="71415976"/>
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  <format>
    <rpm:license>GPL-2.0-only</rpm:license>
    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
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    <rpm:buildhost>i04-ch1c</rpm:buildhost>
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<package type="rpm">
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  <summary>Yosys open synthesis suite</summary>
  <description>This is a framework for RTL synthesis tools. It currently has
extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the yosys C++
code base.

Yosys is free software licensed under the ISC license (a GPL
compatible license that is similar in terms to the MIT license
or the 2-clause BSD license).</description>
  <packager></packager>
  <url>https://yosyshq.net/yosys/</url>
  <time file="1762255167" build="1762254313"/>
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    <file>/usr/bin/yosys</file>
    <file>/usr/bin/yosys-abc</file>
    <file>/usr/bin/yosys-config</file>
    <file>/usr/bin/yosys-filterlib</file>
    <file>/usr/bin/yosys-smtbmc</file>
    <file>/usr/bin/yosys-witness</file>
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</package>
<package type="rpm">
  <name>yosys</name>
  <arch>src</arch>
  <version epoch="0" ver="0.58" rel="11.1.157aabb58"/>
  <checksum type="sha256" pkgid="YES">968629ce9bbe6fa2d008f72387556f8091ef972f3a1c911ac16bb1dc03375f0c</checksum>
  <summary>Yosys open synthesis suite</summary>
  <description>This is a framework for RTL synthesis tools. It currently has
extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the yosys C++
code base.

Yosys is free software licensed under the ISC license (a GPL
compatible license that is similar in terms to the MIT license
or the 2-clause BSD license).</description>
  <packager></packager>
  <url>https://yosyshq.net/yosys/</url>
  <time file="1762255167" build="1762254313"/>
  <size package="9793121" installed="9857477" archive="9857856"/>
  <location href="src/yosys-0.58-11.1.157aabb58.src.rpm"/>
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    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
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</package>
<package type="rpm">
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  <summary>Yosys open synthesis suite</summary>
  <description>This is a framework for RTL synthesis tools. It currently has
extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the yosys C++
code base.

Yosys is free software licensed under the ISC license (a GPL
compatible license that is similar in terms to the MIT license
or the 2-clause BSD license).</description>
  <packager></packager>
  <url>https://yosyshq.net/yosys/</url>
  <time file="1786407160" build="1786405680"/>
  <size package="18992883" installed="19063296" archive="19063676"/>
  <location href="src/yosys-0.68-24.1.38e001a6f.src.rpm"/>
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</package>
<package type="rpm">
  <name>yosys</name>
  <arch>x86_64</arch>
  <version epoch="0" ver="0.68" rel="24.1.38e001a6f"/>
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  <summary>Yosys open synthesis suite</summary>
  <description>This is a framework for RTL synthesis tools. It currently has
extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the yosys C++
code base.

Yosys is free software licensed under the ISC license (a GPL
compatible license that is similar in terms to the MIT license
or the 2-clause BSD license).</description>
  <packager></packager>
  <url>https://yosyshq.net/yosys/</url>
  <time file="1786407160" build="1786405680"/>
  <size package="16684382" installed="59192426" archive="59252480"/>
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    <file>/usr/bin/yosys</file>
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<package type="rpm">
  <name>yosys-debuginfo</name>
  <arch>aarch64</arch>
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  <summary>Debug information for package yosys</summary>
  <description>This package provides debug information for package yosys.
Debug information is useful when developing applications that use this
package or when debugging this package.</description>
  <packager></packager>
  <url>https://yosyshq.net/yosys/</url>
  <time file="1762255167" build="1762254313"/>
  <size package="255687" installed="1854920" archive="1856256"/>
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<package type="rpm">
  <name>yosys-slang</name>
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  <summary>SystemVerilog frontend for Yosys</summary>
  <description>yosys-slang is  a Yosys plugin  providing a new  command (read_slang)
for loading SystemVerilog designs.
  yosys-slang  builds   on  top  of  the  slang  library  to  provide
comprehensive   SystemVerilog  support.   The   plugin  supports   an
(informally defined) synthesizable subset of SystemVerilog in version
IEEE 1800-2017 or IEEE 1800-2023.</description>
  <packager></packager>
  <url>https://github.com/povik/yosys-slang.git</url>
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      <rpm:entry name="libm.so.6(GLIBC_2.29)(64bit)"/>
      <rpm:entry name="libm.so.6(GLIBC_2.35)(64bit)"/>
      <rpm:entry name="libstdc++.so.6()(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.15)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.2)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.5)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.7)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.8)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.9)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.11)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.14)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.17)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.18)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.19)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.20)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.21)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.22)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.26)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.29)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.30)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.32)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.9)(64bit)"/>
      <rpm:entry name="rtld(GNU_HASH)"/>
      <rpm:entry name="yosys" flags="GE" epoch="0" ver="0.44"/>
      <rpm:entry name="libc.so.6(GLIBC_2.34)(64bit)"/>
    </rpm:requires>
  </format>
</package>
<package type="rpm">
  <name>yosys-slang</name>
  <arch>src</arch>
  <version epoch="0" ver="2025.10.31.ba1859e" rel="19.1"/>
  <checksum type="sha256" pkgid="YES">46176a85084cfc3bdff6644aa02e068a4478e55c9037bf52af7856506fdf2a95</checksum>
  <summary>SystemVerilog frontend for Yosys</summary>
  <description>yosys-slang is  a Yosys plugin  providing a new  command (read_slang)
for loading SystemVerilog designs.
  yosys-slang  builds   on  top  of  the  slang  library  to  provide
comprehensive   SystemVerilog  support.   The   plugin  supports   an
(informally defined) synthesizable subset of SystemVerilog in version
IEEE 1800-2017 or IEEE 1800-2023.</description>
  <packager></packager>
  <url>https://github.com/povik/yosys-slang.git</url>
  <time file="1762266967" build="1762265260"/>
  <size package="2526120" installed="2520555" archive="2520956"/>
  <location href="src/yosys-slang-2025.10.31.ba1859e-19.1.src.rpm"/>
  <format>
    <rpm:license>ISC</rpm:license>
    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
    <rpm:group>Applications/Engineering</rpm:group>
    <rpm:buildhost>i03-armsrv1</rpm:buildhost>
    <rpm:sourcerpm></rpm:sourcerpm>
    <rpm:header-range start="4504" end="8822"/>
    <rpm:provides>
      <rpm:entry name="yosys-slang" flags="EQ" epoch="0" ver="2025.10.31.ba1859e" rel="19.1"/>
    </rpm:provides>
    <rpm:requires>
      <rpm:entry name="cmake"/>
      <rpm:entry name="gcc-c++"/>
      <rpm:entry name="pkgconfig"/>
      <rpm:entry name="python3"/>
      <rpm:entry name="tcl-devel" flags="GE" epoch="0" ver="8.0.0"/>
      <rpm:entry name="yosys" flags="GE" epoch="0" ver="0.44"/>
    </rpm:requires>
  </format>
</package>
<package type="rpm">
  <name>yosys-slang</name>
  <arch>src</arch>
  <version epoch="0" ver="2025.10.31.ba1859e" rel="20.8"/>
  <checksum type="sha256" pkgid="YES">41bbdb7ce2828fbf7fda6b4793c74e6673ba817bc6810aadb42402df6f35340f</checksum>
  <summary>SystemVerilog frontend for Yosys</summary>
  <description>yosys-slang is  a Yosys plugin  providing a new  command (read_slang)
for loading SystemVerilog designs.
  yosys-slang  builds   on  top  of  the  slang  library  to  provide
comprehensive   SystemVerilog  support.   The   plugin  supports   an
(informally defined) synthesizable subset of SystemVerilog in version
IEEE 1800-2017 or IEEE 1800-2023.</description>
  <packager></packager>
  <url>https://github.com/povik/yosys-slang.git</url>
  <time file="1786408563" build="1786407561"/>
  <size package="2526163" installed="2520633" archive="2521036"/>
  <location href="src/yosys-slang-2025.10.31.ba1859e-20.8.src.rpm"/>
  <format>
    <rpm:license>ISC</rpm:license>
    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
    <rpm:group>Applications/Engineering</rpm:group>
    <rpm:buildhost>i03-ch2b</rpm:buildhost>
    <rpm:sourcerpm></rpm:sourcerpm>
    <rpm:header-range start="4504" end="8824"/>
    <rpm:provides>
      <rpm:entry name="yosys-slang" flags="EQ" epoch="0" ver="2025.10.31.ba1859e" rel="20.8"/>
    </rpm:provides>
    <rpm:requires>
      <rpm:entry name="cmake"/>
      <rpm:entry name="gcc-c++"/>
      <rpm:entry name="pkgconfig"/>
      <rpm:entry name="python3"/>
      <rpm:entry name="tcl-devel" flags="GE" epoch="0" ver="8.0.0"/>
      <rpm:entry name="yosys" flags="GE" epoch="0" ver="0.44"/>
    </rpm:requires>
  </format>
</package>
<package type="rpm">
  <name>yosys-slang</name>
  <arch>x86_64</arch>
  <version epoch="0" ver="2025.10.31.ba1859e" rel="20.8"/>
  <checksum type="sha256" pkgid="YES">00c200199693c0fae68576e5ee34e19c7632f468c4d101c16c423ffeef497f99</checksum>
  <summary>SystemVerilog frontend for Yosys</summary>
  <description>yosys-slang is  a Yosys plugin  providing a new  command (read_slang)
for loading SystemVerilog designs.
  yosys-slang  builds   on  top  of  the  slang  library  to  provide
comprehensive   SystemVerilog  support.   The   plugin  supports   an
(informally defined) synthesizable subset of SystemVerilog in version
IEEE 1800-2017 or IEEE 1800-2023.</description>
  <packager></packager>
  <url>https://github.com/povik/yosys-slang.git</url>
  <time file="1786408563" build="1786407561"/>
  <size package="2141107" installed="7315685" archive="7316396"/>
  <location href="x86_64/yosys-slang-2025.10.31.ba1859e-20.8.x86_64.rpm"/>
  <format>
    <rpm:license>ISC</rpm:license>
    <rpm:vendor>obs://build.opensuse.org/home:jpc-lip6</rpm:vendor>
    <rpm:group>Applications/Engineering</rpm:group>
    <rpm:buildhost>i03-ch2b</rpm:buildhost>
    <rpm:sourcerpm>yosys-slang-2025.10.31.ba1859e-20.8.src.rpm</rpm:sourcerpm>
    <rpm:header-range start="4504" end="9785"/>
    <rpm:provides>
      <rpm:entry name="yosys-slang" flags="EQ" epoch="0" ver="2025.10.31.ba1859e" rel="20.8"/>
      <rpm:entry name="yosys-slang(x86-64)" flags="EQ" epoch="0" ver="2025.10.31.ba1859e" rel="20.8"/>
    </rpm:provides>
    <rpm:requires>
      <rpm:entry name="libgcc_s.so.1()(64bit)"/>
      <rpm:entry name="libgcc_s.so.1(GCC_3.0)(64bit)"/>
      <rpm:entry name="libgcc_s.so.1(GCC_3.3.1)(64bit)"/>
      <rpm:entry name="libm.so.6()(64bit)"/>
      <rpm:entry name="libm.so.6(GLIBC_2.2.5)(64bit)"/>
      <rpm:entry name="libm.so.6(GLIBC_2.27)(64bit)"/>
      <rpm:entry name="libm.so.6(GLIBC_2.29)(64bit)"/>
      <rpm:entry name="libm.so.6(GLIBC_2.35)(64bit)"/>
      <rpm:entry name="libstdc++.so.6()(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.15)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.2)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.5)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.7)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.8)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(CXXABI_1.3.9)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.11)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.14)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.17)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.18)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.19)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.20)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.21)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.22)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.26)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.29)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.30)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.32)(64bit)"/>
      <rpm:entry name="libstdc++.so.6(GLIBCXX_3.4.9)(64bit)"/>
      <rpm:entry name="rtld(GNU_HASH)"/>
      <rpm:entry name="yosys" flags="GE" epoch="0" ver="0.44"/>
      <rpm:entry name="libc.so.6(GLIBC_2.34)(64bit)"/>
    </rpm:requires>
  </format>
</package>
</metadata>